Advanced examples

These examples combine reusable components, protocol and register models, generated artifacts, richer data types, and production-scale RTL. Each one is a complete, runnable project with a pure-SystemVerilog twin.

Example	Start here for	Source shown
Component FIFO	Reusable transaction endpoints and analysis fan-out	Complete component composition
APB register file	Optional protocol component package	Generic sequence, master, monitor, checker, scoreboard, and coverage
APB transaction trace	Timed typed transaction recording	256-operation monitor, scoreboard, in-memory trace, and JSON Lines output
IP-XACT register model	A standard IP-XACT contract with registers and native memory	Generated hierarchy, fake-master check, APB sequence, and pure-SV peer
Fault injection	Internal access and controlled fault injection	Deposit, force, release, and ReadOnly settling
Rich data	Wide, fixed-point, array, struct, and enum ports	Typed construction and checking
Interfaces and inouts	Parameterized interfaces, modports, interface arrays, and bidirectional pins	Named member access, independent clocks, drive, and release
Mixed-language logging	One ordered C++ and RTL diagnostic stream	C++ loggers, SV macros, source provenance, and hierarchy
Heavy benchmarks	Computationally substantial four-mode comparisons	FIR, packet CRC32, and matrix accelerator sequences
Open-source cores	Real CPU, crypto, and network RTL comparisons	Firmware, register programming, and AXI-stream sequences
secworks AES register-model oracle	Ground-truth validation of generated register access	Upstream oracle, generated RegModel, and matched pure-SV sequence

Fault injection is the smallest complete bench centred on internal hierarchy access — deposit, force, release, and settling against inferred RTL objects, with no probe list. Read it alongside Hierarchical DUT access.