Clockless timers

Not every design has a clock to wait on. Delay advances absolute simulation time on its own, so a combinational or purely time-driven model needs no clock registration at all:

uv run --frozen cpptb build --project examples/timer_only --build-dir build

Two independent cadences share one fixed semantic workload and are joined by the registered test:

constexpr uint32_t kCadenceSamples = 9;

Task<void> timer_only_test(Dut dut, TestContext& test) {
    co_await Join{fast_cadence(dut, test), slow_cadence(dut, test)};

    test.expect_eq("timer-only final absolute time",
                   test.now().in_picoseconds(),
                   static_cast<uint64_t>(kCadenceSamples) * 11'000u + 1u);
}

CPPTB_REGISTER_TEST(timer_only_test);

Each write is followed by an explicit Delay{1_ps} before sampling. The write itself does not advance simulation time. The pure SV peer mirrors kCadenceSamples = 9 and the same #1ps settle points.

make cpp-dpi-timer-only-run
make cpp-dpi-timer-only-sv-run